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SEMICONDUCTOR TECHNICAL DATA
Freescale Semiconductor, Inc.
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DATA SHEET
NOT RECOMMENDED FOR NEW DESIGNS
32 Bit to 32/16/8 Bit 32-Bit to 32/16/8-Bit Dynamic Dynamic READ/WRITE Bus Sizer Sizer READ/WRITE Bus
The MC68150 Dynamic Bus Sizer is designed to allow the 32-bit MC68/LC/EC040 bus, or other 16- to 32-bit processors, to communicate bi-directionally with 32-, 16-, or 8-bit peripherals and memories. It dynamically recognizes the size of the selected peripheral/memory and then writes or reads the appropriate data to or from that location. Systems designed using the bus sizing feature built into the 68030 can now be easily upgraded to the 68/EC040 by incorporating the MC68150. The 68150 comes in two speed grades: 25/33MHz and 40MHz. These frequencies correspond to their 68040 counterparts. The two grades should be ordered as the MC68150FN33 and MC68150FN40, respectively. Typical operations which call for bus sizing are booting up instructions from 8-bit ROM (EPROM, EEPROM, etc.) and communicating with 8-bit SRAM's for scratch pad memory storage during interrupt operations. The dynamic property is necessary because the processor does not always know the size of the peripheral it is accessing, as in the case of communicating with a 16-bit VME bus. The MC68150 can also be used to separate a 32-bit "Fast Bus" and an 8-, 16-, or 32-bit "Slow Bus". (See Figure 3) Features
MC68150
MC68150
DYNAMIC READ/WRITE BUS SIZER
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26 61
9
10
* Allows MC68/LC/EC040 or Other `040 Based Controllers or 68060 to
Communicate With 8-Bit Memories and Any MC68XXX Peripheral
* Also Allows Other RISC Processors to Communicate With 8-Bit and
16-Bit Peripherals
* Recognizes the Port (Peripheral) Size Dynamically * Generates Byte/Word Address to the Dynamic Port * Generates Byte WRITE Enable Signals For 16- and 8-bit Ports * Sends a Transfer Acknowledge Signal to the Processor When a
Transfer Is Completed
FN SUFFIX PLASTIC PACKAGE CASE 779-02
EI SUFFIX Plastic Package Case 779-02 (Pb-Free Package)
* Synchronization of Data Transfer on Dynamic Port Allows Use of Any
Speed Peripheral 1. Overview of Chip Operation Each access through the MC68150 is started with a chip select (CS) assertion to the MC68150 - which is generated when a PAL sees a TS signal from the `040 - and completed with a transfer acknowledge (TA) from the MC68150 to the MC68040. The MC68150 has two distinct buses, the MPU bus and the peripheral bus. The MPU bus connects to the processor and includes the transfer control signals (A1, A0, SIZ1, SIZ0, and R/W), the chip select (CS), the transfer acknowledge (TA) and the data bus signals (D31-D0). The peripheral bus consists of the peripheral transfer control signals (SWE, UWE, LWE, DS, PA1, PA0), and the peripheral transfer acknowledge signals (DSACK1, DSACK0) and the peripheral data bus (PD31-PD16). If a 32-bit peripheral bus is used, then two additional transceivers (e.g. MC74F245) are required for the lower two bytes of the data. These transceivers would be connected to the PD15-PD0 pins on the peripheral side and to the corresponding D15-D0 pins on the MPU bus. The transfer direction is controlled with the R/W signal of the processor. The transceivers are enabled only when making an access to a 32-bit port. The D15-D0 pins of the MPU bus on the MC68150 are always disabled until the port size is known, to avoid bus contention when the port is 32-bits. An access refers to the complete transaction through the MC68150. On the peripheral bus, an access is split into one, two, or four separate transfers.
IDTTM11/94 to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer 32-Bit
REV (c) Motorola, Inc. 1994 For More Information On Technology,4Inc. Freescale Timing Solutions Organization has been acquired by Integrated DeviceThis Product,
MC68150 JULY 30, 2009
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1
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
PIN DESCRIPTIONS
Pin BCLK D31-D0 PD31-PD16 PA1, PA0 UWE, LWE SWE DS DSACK1, DSACK0 SIZ1, SIZ0 A1, A0 CS TA R/W I/O I I/O I/O O O O O I
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Description Bus clock -- the main system clock (from MC88916) Data bits on the 32-bit `040 bus Peripheral data -- data bits on the 8/16/32-bit peripheral side; PD15-PD0 do not exist for a 32-bit access, these require two F245 transceivers Peripheral address -- address bits indicating the byte being accessed on the peripheral side (00 = MSB, 11 = LSB) Upper (PD31-PD24), lower (PD23-PD16) write enables on the peripheral side significant for 16-bit ports (WRITE) Single write enable on the peripheral-bit side for 8-bit ports (WRITE) Data strobe indicates data can be put on the peripheral bus to be read by the `040 (READ) or is valid to be written on the peripheral bus (WRITE) Data transfer acknowledge. HH inserts wait states in the current bus cycle. HL indicates the peripheral bus size is 8-bits. LH indicates peripheral bus size is 16-bits. LL indicates the peripheral bus is 32-bits. Recognition of these signals is what allows for "dynamic" bus sizing Indicates the size of the MPU bus access. HH or LL = 32-bits (long word); HL = 16-bits (word); LH = 8-bits (byte) `040 Address bits, Indicates the byte offset of the `040 access (which byte is accessed: HH = D7-D0; HL = D15-D8; LH = D23-D16; LL = D31-D24) Chip select, tells the 68150 that a transfer is starting or ending Transfer acknowledge indicates the 68150 has completed the transfer READ/WRITE, tells the 68150 if it is a read or write transfer D7 60 D6 59 D5 58 D4 57 D3 56 D2 55 D1 54 D0 GND PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 VCC PA1 PA0 UWE LWE SWE DSACK1 DSACK0 DS
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I I I O I
D8 D9 D10 D11 D12 D13 D14 D15 VCC D16 D17 D18 D19 D20 D21 D22 D23
61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 TA
MC68150
35 34 33 32 31 30 29 28 27
D24 D25 D26 D27 D28 D29 D30 D31 GND A1
A0 SIZ1 SIZ0 R/W BCLK CS
Figure 1. Pinout: 68-Lead PLCC (Top View)
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MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
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MC74F245
B7 - B0 T/R A7 - A0 OE PD7 - PD0 CS32L PD7 - PD0 PD15 - PD8 PD23 - PD16 A7 - A0 OE PD15 - PD8 CS32L PD31 - PD24 A31 - A2
NETCOM
MC68150
32 BIT PORT
D7 - D0 D15 - D8 D23- D16 D31 - D24 A2 - Ax A0 A1 SIZ0 SIZ1
MC74F245
B7 - B0 T/R
MC68EC040
MC68150
D7 - D0 D15 - D8 D23 - D16 D31 - D24 R/W SIZ0 SIZ1 A0 A1 UWE LWE SWE TA from rest of system DSACK1 CS BCLK DSACK0 DS PA1 PA0 PD23 - PD16 PD31 - PD24
SWE CS32
R/W CS
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D7 - D0 D15 - D8 D23 - D16 D31 - D24 R/W SIZ0 SIZ1 A0 A1
32 BIT PORT
PD7 - PD0 PD15 - PD8 PD23 - PD16 PD31 - PD24 A31 - A2 UWE LWE UWE LWE CS32L CS32U D7 - D0 D15 - D8 D23- D16 D31 - D24 A0 - Ax W(D31 - D24) W(D23- D16) W(D15 - D8) W(D7- D0) CS(D15- D0) CS(D31 - D16)
F08 or PAL
TA
TA
TBI
MC88916
Q1 BCLK PCLK RSTI Q0 2x_Q RST_OUT Q2
16 BIT PORT
PD31 - PD24 PD23 - PD16 PA1 A31 - A2 UWE LWE D15 - D8 D7 - D0 A0 A1 - Ax W(D15 - D8) W(D7- D0) CS
PAL
DS CLK TA_68150 CS_68150
CS16
8 BIT PORT
PD31 - PD24 D7 - D0 A1 A0 A2 - Ax W CS
DSACK0 DSACK1 CS32 CS32L CS32U PA1 PA0 A31 - A2 SWE CS8
A31 - A2 TS
A31 - Ax TS
CS16 CS8
Figure 2. MC68150 Typical System Configuration
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MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
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SLOW Bus" 32 8 MC68150 BUS SIZER 16 16 BIT PORTS
NETCOM
8 BIT PORTS
PROCESSOR
(Isolate slower bus from FAST Bus") TRANSCEIVERS FAST Bus" 32 DYNAMIC RAM
16 16
32 BIT PORTS
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Figure 3. "FAST Bus" "SLOW Bus" Application
Table 1. 68150 TRUTH TABLE (READ Mode)
SIZ1 L L L L L L L L L L L L H H H H H H H H SIZ0 H H H H H H H H H H H H L L L L L L L L PA1 L L H H L L H H L L H H L H L H L L H H X L H L L H H PA0 L H L H L H L H L H L H X X X X L H L H X X X L H L H DSACK1 L L L L L L L L H H H H L L L L H H H H L L L H H H H DSACK0 L L L L H H H H L L L L L L H H L L L L L H H L L L L D31:24 Out0 X X X Out0 X X X Out0 X X X Out0 X Out0 X Out0 . X X Out0 Out0 . Out0 . . . D23:16 X Out1 X X X Out1 X X X Out1 X X Out1 X Out1 X X Out1 X X Out1 Out1 . X Out1 . . D15:8 Z Z Z Z X X Out2 X X X Out2 X Z Z X Out2 X X Out2 . Z X Out2 X X Out2 . D7:0 Z Z Z Z X X X Out3 X X X Out3 Z Z X Out3 X X X Out3 Z X Out3 X X X Out3 PD31:24 In0 X X X In0 X In2 X In0 In1 In2 In3 In0 X In0 In2 In0 In1 In2 In3 In0 In0 In2 In0 In1 In2 In3 PD23:16 X In1 X X X In1 X In3 X X X X In1 X In1 In3 X X X X In1 In1 In3 X X X X 16-Bit READ from 8-Bit Peripheral (2 Transfers) 16-Bit READ from 8-Bit Peripheral (2 Transfers) 32-Bit READ from 32-Bit Peripheral 32-Bit READ from 16-Bit Peripheral (2 Transfers) 32-Bit READ from 8-Bit Peripheral (4 Transfers) 13 17 15 23 16-Bit READ from 16-Bit Peripheral 16-Bit READ from 32-Bit Peripheral 8-Bit READ from 8-Bit Peripheral 8-Bit READ from 16-Bit Peripheral Description of Transfer 8-Bit READ from 32-Bit Peripheral Fig 49 51 53 55 41 43 45 47 33 35 37 39 29 31 25 27 21
LL or HH LL or HH LL or HH LL or HH LL or HH LL or HH LL or HH
X = Don't Care (Do Not Leave Inputs Floating); . = Latched Data From Peripheral; Z = 3-State; InX = Input (0 Signifies the MSB and 3 Signifies the LSB); OutX = Output Corresponding to the Input InX
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MC68150
Table 2. 68150 TRUTH TABLE (WRITE Mode)
SIZ1 L L L L L L L L L L L L SIZ0 H H H H H H H H H H H H L L L L L L L L PA1 L L H H L L H H L L H H L H L H L L H H X L H L L H H PA0 L H L H L H L H L H L H X X X X L H L H X X X L H L H DSACK1 L L L L L L L L H H H H L L L L H H H H L L L H H H H DSACK0 L L L L H H H H L L L L L L H H L L L L L H H L L L L D31:24 In0 X X X In0 X X X In0 X X X In0 X In0 X In0 . X X In0 In0 . In0 . . . D23:16 X In1 X X X In1 X X X In1 X X In1 X In1 X In1 . X X In1 In1 . In1 . . . D15:8 X X In2 X X X In2 X X X In2 X X In2 X In2 X X In2 . In2 In2 . In2 . . . D7:0 X X X In3 X X X In3 X X X In3 X In3 X In3 X X In3 . In3 In3 . In3 . . . PD31:24 Out0 X X X Out0 X Out2 X Out0 Out1 Out2 Out3 Out0 X Out0 Out2 Out0 Out1 Out2 Out3 Out0 Out0 Out2 Out0 Out1 Out2 Out3 PD23:16 X Out1 X X X Out1 X Out3 X X X X Out1 X Out1 Out3 X X X X Out1 Out1 Out3 X X X X 16-Bit WRITE to 8-Bit Peripheral (2 Transfers) 16-Bit WRITE to 8-Bit Peripheral (2 Transfers) 32-Bit WRITE to 32-Bit Peripheral 32-Bit WRITE to 16-Bit Peripheral (2 Transfers) 32-Bit WRITE to 8-Bit Peripheral (4 Transfers) 14 18 16 24 16-Bit WRITE to 16-Bit Peripheral 16-Bit WRITE to 32-Bit Peripheral 8-Bit WRITE to 8-Bit Peripheral 8-Bit WRITE to 16-Bit Peripheral Description of Transfer 8-Bit WRITE to 32-Bit Peripheral Fig 50 52 54 56 42 44 46 48 34 36 38 40 30 32 26 28 22
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H H H H H H H H
LL or HH LL or HH LL or HH LL or HH LL or HH LL or HH LL or HH
X = Don't Care (Do Not Leave Inputs Floating); . = Latched Data From Processor; Z = 3-State; InX = Input (0 Signifies the MSB and 3 Signifies the LSB); OutX = Output Corresponding to the Input InX
TYPICAL SYSTEM CONFIGURATION
A 68040 system using the MC68150 for dynamic bus sizing consists minimally of the MC68040 microprocessor, the MC68150, a PAL for timing control, and various size memory devices. When a 32-bit port is required, two F245's must be used to buffer the PD15-PD0 bits to the D15-D0 bits of the `040, since the MC68150 does not support these bits. The typical system configuration (Figure 2) illustrates communication between a 68040 and 8-, 16-, and 32-bit peripheral chips.
Design Guidelines * Peripheral data connections are the same as for a 68030
- - - - - - - Connect PD31:24 for 8-bit port Connect PD31:24 for upper byte 16-bit port Connect PD23:16 for lower byte 16-bit port Connect PD31:24 for upper-upper byte 32-bit port Connect PD23:16 for upper-middle byte 32-bit port Connect PD15:8 for lower-middle byte 32-bit port Connect PD7:0 for lower-lower byte 32-bit port
* 32-bit ports require transceivers or latched transceivers for PD15:0
- The MC68150 only passes the upper 16 data bits on a 32-bit transfer
* 68150 does not support burst mode
- One way to handle this is to connect TA of the 68150 to TBI of the 68040
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MC68150
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MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
2. MC68040 BUS OPERATION
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An access is divided into multiple states. Each state represents half a clock period. All even states are defined when BCLK is High, all odd states are defined when BCLK is low. A clock edge is referenced by the state that follows the clock edge. All rising edges are referenced by even number states. All falling edges are referenced by odd number states. DS0 is the first state of an access. DSW represents a wait state or a mid-access transfer state. A wait state indicates an access is occurring, but that the MC68150 is waiting on the peripheral to complete the transaction. Note that the peripheral and MPU states are distinct, though related, to each other. The peripheral states start with S0. Figure 4 is an example transfer with the states marked.
2.1 Access Start The MC68040 begins an access by asserting the transfer control signals and transfer start (TS). The transfer control signals are held by the MC68040 throughout the access. The transfer start is asserted around only one rising edge of the clock (BCLK). The chip select (CS) for the MC68150 is asserted while the MC68040 transfer control signals are input to the MC68150. The transfer control signals (A1, A0, SIZ1, SIZ0, R/W) must all be valid a set-up time before the rising edge of BCLK on which CS recognized (DS2). If the transfer control signals change states during this set-up time, the MC68150 operation is unpredictable. The transfer control signals must be held valid until at least DS4. If the CS switches during the set-up time before the rising edge of DS2, then the access may not be recognized until the next clock edge. Once asserted, CS must be held asserted until the end of the access. During a write access, the data signals (D(31:0)) must be valid a set-up time before the rising edge of DS2. The `040 data is latched into the 68150 off the DS2 rising clock edge (as long as CS is recognized as described above). This latched data is internally held by the 68150 until CS is negated at the end of a transfer.
DS0 DS1 DS2 DS3 DS4 DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DS5 DS6 DS7 DS8 DS9 DS10 BCLK CS TRANSFER CONTROLS D(31:0) [WRITE] D(31:16) [READ] D(16:0) [READ] TA PA(1:0) PD(31:24) [WRITE] PD(31:24) [READ] DS UWE, LWE, SWE DSACK1, DSACK0 = Driven but undefined. Transfer Controls = A1, A0, SIZ1, SIZ0 and R/W S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18
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Figure 4. MC68150 32-Bit to 8-Bit Transfer Example (READ or WRITE)
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MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
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MC68150
2.2 Early Access Termination An access through an MC68150 can be terminated before completion by negating CS early. The CS negation is recognized on a rising edge of BCLK. The CS early negation is used when the access should be ignored, such as when a bus error occurs. Any data transferred through the MC68150 is lost when an early access negation occurs. If the access must be completed at a later time, the entire access must be repeated. To guarantee that TA is not asserted during early negation, CS must be negated before DS6. For peripherals that can be read or written to twice, special care must be taken in aborting the 68150 access. 2.3 Early Release of the MPU Bus Though early MPU bus release is not economical for most applications, it may allow an incremental improvement in performance at the expense of additional logic. The transfer control signals (A1, A0, SIZ1, SIZ0, R/W) are held valid at least until DS4. During a write access, the data signals are held valid at least until DS4. After this hold time, the transfer control signals may change without affecting operation as long as CS remains asserted. This allows the MC68150 to release the MPU bus before the access is complete on the peripheral side of the MC68150. During a read access, early release is of limited use, because the MC68040 will not be able to use the bus until the peripheral data has been read. On a write, early MPU bus release does allow the MC68040 to continue with the next operation while the MC68150 completes the access. When using this early release feature, a bus error could be difficult to handle. If the peripheral asserts a bus error after the MC68040 receives a TA, meaning the transfer is complete, then a subsequent bus error assertion to the MC68040 will not match the offending address with the bus error address. This can be handled by software or hardware that reads a bit to see if the bus error is coming from the MC68150. Another consideration in using early bus release is the handling of back to back transfers and transfer acknowledges. The chip select logic for the MC68150 must recognize when a second access occurs while completing an access on the peripheral side. The CS must be negated for one rising edge of BCLK between accesses. The transfer acknowledge from the MC68150 signals the end of the access. If early bus release is used, then the transfer acknowledge generated by the MC68150 should not be sent to the MC68040.
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(16:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER SECOND TRANSFER ACCESS END 00 10 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DSW S5 DSW S6 DSW S7 DSW S8 DS5 S9 DS6 DS7 DS8 DS9 DS10 DS11
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Figure 5. 32-Bit `040 READ from 16-Bit Peripheral With Asynchronous Termination
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MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
2.4 Access Termination
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The final transfer on the peripheral side of the MC68150 occurs during DS5. The MC68150 access is normally terminated by the MC68150 asserting TA during DS6. Once the TA is asserted, TA is held asserted until at least DS8. The MC68150 negates TA asynchronously if CS is negated after DS7; an example of asynchronous termination is shown in Figure 5. An abnormal MC68150 termination occurs when the CS is negated before DS6. See early access termination for more details. For a normal access, CS is held asserted until at least DS6. TA negation is synchronous to the rising edge of DS8 if CS meets a set-up to a DS8 rising BCLK edge. Asynchronous termination is defined as any CS negation beyond the DS8 rising BCLK edge. In this case the TA occurs a delay after the CS negation, because it is asynchronous termination. During a read access, the data being presented to the MC68040 is held for at least one rising edge of BCLK (DS8). When CS is negated, the MPU data bus goes to high impedance. If the data must be held longer than a single period, then asynchronous TA negation is necessary.
2.5 MPU Bus Idle State
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CS must remain high for one rising edge of BCLK between each access. This is guaranteed by the MC68040 if CS is asserted on the clock edge following TS assertion (or later) on all accesses through the MC68150. When the MPU bus is idle (between accesses), the D(31:0) are in high impedance and TA is negated.
3. PERIPHERAL BUS OPERATION
The peripheral access is divided into one or more transfers. The transfers are divided into multiple states. Each state represents half a clock period. All even states are the BCLK HIGH half of the clock period. All odd states are the BCLK LOW half of the clock period. A clock edge is referenced by the state that follows the clock edge. All rising edges are referenced by even number states. All falling edges are referenced by odd number states. S0 is the first state of a peripheral access. Note that the peripheral and MPU states are distinct, though related to each other.
3.1 Initial Transfer Start A transfer starts off the rising edge of BCLK following the CS assertion (S2). The starting address of the transfer (PA1, PA0) is asserted during S2. The MC68040 A(31:2) are routed past the MC68150, directly to the peripheral bus. Buffers can be used to minimize loading on the MC68040 address bus. If the access is a write, the peripheral data bus (PD(31:16)) is driven during S2. The starting data strobe (DS) is asserted during S3. If the access is a write, the starting write enables (SWE, UWE, and LWE) are also asserted during S3. SWE is the write enable for 8-bit peripherals. The SWE is asserted for every transfer of a write access. It indicates the data on PD(31:24) is valid and ready to be written to the 8-bit peripheral. UWE and LWE are the write enables for 16-bit peripherals. UWE indicates the data on PD(31:24) is valid and ready to be written to the 16-bit peripheral. LWE indicates the data on PD(23:16) is valid and ready to be written to the 16-bit peripheral. A 32-bit port can generate write enables from the MC68040 normally (A1, A0, SIZ1, SIZ0 and R/W). These write enables can be qualified with SWE or DS for the 32-bit peripheral. An alternative is to use the UWE and LWE in conjunction with the PA1 and PA0. If it is a 32-bit access (SIZ1 and SIZ0 = HH or LL), then apply UWE to PD(31:24), PD(15:8) and LWE to PD(23:16), PD(7:0). If it is a 16-bit access (SIZ1 and SIZ0 = HL), then apply UWE to PD(31:24) and LWE to PD(23:16).
3.2 Initial Transfer Termination Starting with S2, the MC68150 monitors the data strobe acknowledge signals (DSACK1, DSACK0) for the access termination. Wait states are inserted into the access by maintaining DSACK1 and DSACK0 HIGH. The DSACK1 and DSACK0 are sampled on the falling edge of BCLK. DSACK1 and DSACK0 must remain valid for two successive falling edges of BCLK to be recognized. If the access is a read, the PD(31:16) must be valid a set-up before the falling edge between S4 and S5. The PD(31:16) must be held valid a hold time into S5. The DSACK1 and DSACK0 are first sampled during S2. The DSACK1 and DSACK0 are then continuously sampled each falling edge of BCLK until the entire access is completed. This means the fastest initial transfer is two clocks (starting S2 and ending S4). The size of the peripheral port is indicated by the DSACK1 and DSACK0. The port size must be indicated on the first transfer and is the port size for the remainder of the access. Once the peripheral port size is indicated on the first transfer, all subsequent transfers should be terminated with the same port size indication. If another port size is indicated on subsequent transfers of the same access, the MC68150 operation is not guaranteed nor predictable. Depending upon the conditions, the MC68150 may either
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MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
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MC68150
ignore the port size change on subsequent transfers or accept the subsequent transfers as a transfer of the original port size. If the MC68150 ignored the improper transfer, the DS is not negated. If the MC68150 accepted the improper transfer as an original port size transfer, DS negates normally. If a different port size is indicated on subsequent transfers, the changing of DSACK1 and DSACK0 states on subsequent transfers may or may not insert wait states into the access. When a valid DSACK1 and DSACK0 state has been held for two consecutive falling edges of BCLK, the intial transfer is ended (falling edges of S3 and S5). DS is negated during S5. If the access is a write, SWE, UWE and LWE are all negated during S5. PA1 and PA0 are held valid until S6. If the access is a write, PD(31:16) are held valid until S6. Table 3. DSACK1 AND DSACK0 DECODE LOGIC
CS H L L L L DSACK1 X L L H H DSACK0 X L H L H No Access Complete 32-Bit Access Complete 16-Bit Access Complete 8-Bit Access Insert Wait States
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3.3 Subsequent Access Termination If additional transfers are required to complete an access (e.g. a long word access to a byte port requires four transfers to complete), then PA1 and PA0 are changed during S6. If the access is a write, PD(31:16) is changed during S6. DS, SWE, UWE and LWE are asserted during S7. The DSACK1 and DSACK0 are sampled again for the subsequent transfer during S6. If the access is a read, the PD(31:16) must be valid a set-up before the falling edge between S8 and S9. The PD(31:16) must be held valid a hold time into S9. DS, SWE, UWE and LWE are negated during S9. Subsequent transfers continue in the same manner with S10 and S14 replacing S6 above, S11 and S15 replacing S7 above, S13 and S17 replacing S9 above, and S14 and S18 replacing S10. Figures 13 and 14 are examples of 32-bit `040 access from/to an 8-bit port, read and write respectively. Both require four sequential data transfers to complete the access. On a write, the PD(31:16) bus goes into high impedance when TA asserts (DS6). To hold the data valid on the PD(31:16) bus beyond the normal access end, wait states must be inserted using DSACK1, DSACK0 = HH on the last transfer. The wait states will delay TA assertion. 3.4 Peripheral Bus Idle State The MC68150 enters an idle state on the peripheral bus on the rising edge of BCLK after the last transfer is terminated. When the peripheral bus is idle, DS, UWE, LWE and SWE are all negated. PA1 and PA0 are driven, but undefined. PD(31:16) are in high impedance. DSACK1 and DSACK0 are ignored.
3.5 Peripheral Bus Asynchronous Operation (Only for operation independant of BCLK non-680X0 processors. See AC Specifications 22-34 in lieu of specs 1-21) The MC68150 peripheral bus has both asynchronous and sychronous operations. The asynchronous operation allows the user to operate the peripheral bus independently of the BCLK. The synchronous operation requires close attention to the BCLK set-up and hold times. An asynchronous transfer on the MC68150 begins with the assertion of DS by the MC68150. If the access is a write, SWE, UWE and LWE are asserted at the same time as DS. PA1 and PA0 are valid before the DS assertion. PD(31:16) are driven and valid before DS assertion. To avoid bus contention on the peripheral bus, the R/W from the MPU can be used. The DSACK1 and DSACK0 assertions must be within the asynchronous skew specification. If one of the DSACK signals is asserted on one falling edge, the asynchronous skew specification ensures that the other DSACK signal is valid before the next falling edge. Because the DSACK signals can be changing on a falling BCLK edge, an additional wait state may be incurred. DSACK1 and DSACK0 can be negated when DS is negated. If the access is a write, the UWE, LWE and SWE negate at the same time as DS. PD(31:16) change state after the DS, UWE, LWE and SWE are negated. If the access is a read, PD(31:0) is valid after DSACK1 and DSACK0 are asserted and held until DS is negated.
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 9
MC68150
MOTOROLA 9
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT TSTG TA
Freescale Semiconductor, Inc.
NETCOM
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, Per Pin DC Output Sink/Source Current, Per Pin Storage Temperature Range Operating Ambient Temperature Range
Value -0.3 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 20 35 -55 to +150 -40 to +85
Unit V V V mA mA C C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
Freescale Semiconductor, Inc...
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA IOL/IOH Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Ambient Temperature Range Output Current, LOW/HIGH (Control Pins) (Data Pins) Min 4.5 0 -40 Max 5.5 VCC 85 16 5 Unit V V C mA
OTHER CHARACTERISTICS
Symbol CIN COUT CI/O ILATCHUP VESD PD Input Capacitance Output Capacitnace Input/Output Capacitance Latchup Current Electrostatic Discharge Voltage Power Dissipation in Still Air (Calculated at Worst Case) Parameter Conditions VI = 0V or VCC VI = 0V or VCC VI = 0V or VCC >500 8,000 530 Ratings 8.5 Unit pF pF pF mA V mW
NOTE: Rating values are design targets. Actual performance will be noted upon completion of characterization.
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 Go to: www.freescale.com 10
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
NETCOM
MC68150
ICC versus FREQUENCY
No Load (50pF Only) 25C ICC (mA) Frequency (MHz) 1 10 20 30 40 4.5 2 13 25 38 51 5.0 4 16 29 43 59 5.5 6 20 35 50 67 4.5 65 75 85 95 105 Loaded (50pF/500) 25C ICC (mA) 5.0 73 83 95 106 120 5.5 82 93 106 120 135
DC SPECIFICATIONS
Symbol Characteristic Input HIGH Voltage Input LOW Voltage Input Leakage Current SIZ1, SIZ0, A1, A0, CS, DSACK1, DSACK0, R/W, BCLK Hi-Impedance (Off-State) Leakage Current D(31:0), PD(31:16) Additional Maximum ICC/Input BCLK Only Additional Maximum ICC/Input SIZ1, SIZ0, A1, A0, CS, DSACK1, DSACK0, R/W Output High Voltage: VOH Output High Voltage: Output Low Voltage: VOL Output Low Voltage: ICC For DS, SWE, UWE, LWE, PA1, PA0, TA 0.5 100 V A For DS, SWE, UWE, LWE, PA1, PA0, TA For D(31:0), PD(31:16) 2.4 0.5 V V For D(31:0), PD(31:16) 2.4 Min 2.0 GND Max VCC 0.8 20 20 7.5 1.5 Unit V V A A mA mA V Condition VCC = 5V VCC = 5V VIN = 0.5V/2.4V, VCC = 5.25V VIN = VIH/VIL VO = GND/VCC VIH = VCC -2.1V, VCC = 5.25V VIH = VCC -2.1V, VCC = 5.25V IOH = -5.0mA, VCC = 4.75V IOH = -16mA, VCC = 4.75V IOL = +5.0mA, VCC = 4.75V IOL = +16mA, VCC = 4.75V VCC = 5.25V
Freescale Semiconductor, Inc...
VIH VIL IIN IOZ ICCT (BCLK) ICCT
Maximum Quiescent Supply Current
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MC68150
MOTOROLA 11
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
NETCOM
AC SPECIFICATIONS (VCC = 5.0V 10%; TA = -40C to +85C; CL = 50pF; RL = 500)
Spec Number 1 2 3 4 5 6 7 8 9 25MHz Specification/Characteristic CS Asserted to BCLK Rising (Setup) BCLK Rising to CS Negated (Hold) A1, A0, SIZ1, SIZ0, R/W Valid to BCLK Falling (Setup) BCLK Rising to A1, A0, SIZ1, SIZ0, R/W Invalid (Hold) D31:0 Valid to BCLK Rising [WRITE] (Setup) BCLK Rising to D31:0 Invalid [WRITE] (Hold) BCLK Rising to PA1, PA0 Valid (tPLH, tPHL) BCLK Rising to PA1, PA0 Invalid (tPLH, tPHL) PD31:16 Valid to BLCK Falling [READ] (Setup) BCLK Falling to PD31:16 Invalid [READ] (Hold) DSACK1, DSACK0 Valid to BCLK Falling (Setup) BCLK Falling to DSACK1, DSACK0 Invalid (Hold) BCLK Falling to DS, SWE, UWE, LWE (tPLH, tPHL) BCLK Rising to TA (tPLH, tPHL) BCLK Rising D31:16 Low Impedance [READ] (tPZL, tPZH) BCLK Rising to D15:0 Low Impedance [READ] (tPZL, tPZH) BCLK Rising to D31:0 Valid [READ] (tPLH, tPHL) BCLK Rising to D31:16 High Impedance [READ] (tPLZ, tPHZ) BCLK Rising to D15:0 High Impedance [READ] (tPLZ, tPHZ) BCLK Rising to PD31:16 Valid [WRITE] (tPZL, tPZH) BCLK Rising to PD31:16 [WRITE] (tPLH, tPHL) BCLK Rising to PD31:16 High Impedance [WRITE] (tPLZ, tPHZ) DS Asserted to SWE, UWE, LWE Asserted [WRITE] (Skew) DS Negated to SWE, UWE, LWE Negated [WRITE] (Skew) DSACK1, DSACK0, Invalid to DS Negated (tPLH) DS Negated Width SWE, UWE, LWE Negated Width CS to DSACK1, DSACK0 Valid PD31:16 Valid to DS, SWE, UWE, LWE Asserted [WRITE] SWE, LWE, UWE Negated to PD31:16 Invalid [WRITE] DS Negated to PD31:16 High Impedance [WRITE] DS Negated to PD31:16 Invalid [READ] DS, SWE, UWE, LWE Asserted Width CS Negated to D31:16 High Impedance [READ] (tPHZ, tPLZ) CS Negated to D15:0 High Impedance [READ] (tPHZ, tPLZ) PD31:16 Valid to DS Negated [READ] CS Negated to BCLK Rising (Setup) Guarantees Sync Termination BCLK Rising to CS Negated (Hold) Guarantees Async Termination TA Negation to D31:16 High Impedance [READ] (Async Termination) TA Negation to D15:0 High Impedance [READ] (Async Termination) CS Negated to TA Negated (Asynchronous Termination) CS Negated to D31:16 High Impedance [READ] (Async Termination) CS Negated to D15:0 High Impedance [READ] (Async Termination) 2 2 3 38 15 20 8 3 4 11 13 10 16 19 2 2 3 38 38 23 23 27 27 3 42 75 70 28 15 20 8 3 4 10 12 9 15 17 2 2 3 Min 5 2 8 0 3 0 2 2 2 8 4 8 3 2 2 2 0 4 4 2 4 3 10 13 16 16 3 18 22 23 17 19 0.5 1.0 4 42 42 28 28 21 22 26 26 2 32 55 50 23 15 20 8 3 4 9 11 8.5 14 16 12.5 22 Max 33MHz Min 4 1 8 0 2 0 2 2 2 6 2 6 3 2 2 2 0 4 4 2 4 3 9 10 15 15 2 16 20 22 16 18 0.5 1.0 4 32 32 23 23 20 21 25 25 2 27 45 40 10 21 Max 40MHz Min 4 1 8 0 1 0 2 2 2 5.5 2 5 3 2 2 2 0 3 3 2 3 3 9 9 14 14 1 14 19 21 15 17 0.5 1.0 4 27 27 9 20 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Freescale Semiconductor, Inc...
10 11 12 13 14 15 16 17 18a 18b 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33a 33b 34 35 36 37a 37b 38 39a 39b
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 12 Go to: www.freescale.com 12
ASYNCHRONOUS OPERATION ONLY
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MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
NETCOM
MC68150
BCLK 1 CS 2
3 TRANSFER CONTROLS R/W 15 D(31:16) [READ]
4
17
18
Freescale Semiconductor, Inc...
D(15:0) [READ] D(31:0) [WRITE] 5
16
6 14 14
TA 7 PA1,PA0 00 9 PD(31:16) [READ] PD(31:16) [WRITE] 10 9 7 10 10 8
19
20
21
13 DS, SWE
13
UWE, LWE
11 DSACK1
DSACK0 12
BCLK
Figure 6. MC68150 READ/WRITE Timing (Two Transfers Shown for Clarification)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 13
MC68150
MOTOROLA 13
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
NETCOM
BCLK CS
TRANSFER CONTROLS R/W 33 D(31:16) [READ]
Freescale Semiconductor, Inc...
D(15:0) [READ] D(31:0) [WRITE]
TA
PA1,PA0
00 34 31
10 34 31
PD(31:16) [READ] 30 PD(31:16) [WRITE] 28 28 DS, SWE 22 25 23 32 29
UWE, LWE
26
24 DSACK1
32
DSACK0 27
BCLK
Figure 7. MC68150 READ/WRITE Timing; Asynchronous Operation Only for Processors Other Than 680X0 (Two Transfers Shown for Clarification)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 14 Go to: www.freescale.com 14
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MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS6 DS8
NETCOM
MC68150
BCLK CS
35 36 38 39 D(31:16) [READ] 37 D(15:0) [READ]
Freescale Semiconductor, Inc...
D(31:0) [WRITE]
TA
Figure 8. MC68150 READ/WRITE Timing Asynchronous Termination
3V INPUT 1.5V GND tPHL 50% VCC
tPLH OUTPUT
Figure 9. Input/Output Propagation Delays
3V BCLK 1.5V GND tPZL D31:0 PD31:16 1.5V tPZH D31:0 PD31:16 1.5 V HIGH IMPEDANCE tPHZ 10% 90% VOL VOH tPLZ HIGH IMPEDANCE
Figure 10. Enable/Disable Times
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 15
MC68150
MOTOROLA 15
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
NETCOM
VALID 3V INPUT 1.5V tsu BCLK 1.5V GND th GND 3V
Figure 11. Setup/Hold Times
Freescale Semiconductor, Inc...
* Includes all probe and jig capacitance
TEST POINT
OUTPUT DEVICE UNDER TEST RL CL*
Figure 12. Test Circuit
TIMING DIAGRAM EXAMPLES FOR ALL POSSIBLE TRANSFERS
Figures 13 through 56 depict timing waveforms of all possible transfers, including all address combinations. Each pair of figures includes a read transfer and its corresponding write transfer. Figures 13-20 cover all 32-bit `040 bus transfers (to each port size), Figures 21-32 cover all 16-bit `040 bus transfers, and Figures 33-56 cover all 8-bit `040 bus transfers. Specific timing values have been left off these figures; refer to Figures 6-8 and the AC Specifications for this information.
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 16 Go to: www.freescale.com 16
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
NETCOM
MC68150
DS0 DS1 DS2 DS3 DS4 DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DS5 DS6 DS7 DS8 DS9 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER SECOND TRANSFER THIRD TRANSFER FOURTH TRANSFER ACCESS END 00 01 10 11 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
Freescale Semiconductor, Inc...
Figure 13. 32-Bit `040 READ From 8-Bit Peripheral Example
DS0 DS1 DS2 DS3 DS4 DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DSW DS5 DS6 DS7 DS8 DS9 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER SECOND TRANSFER THIRD TRANSFER FOURTH TRANSFER ACCESS END 00 01 10 11 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
Figure 14. 32-Bit `040 WRITE to 8-Bit Peripheral Example
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 17
MC68150
MOTOROLA 17
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 S0
Freescale Semiconductor, Inc.
DS2 S2 DS3 DS4 S4 DSW S5 DSW S6 DSW S7 DSW S8 DS5 S9 DS6 DS7 DS8 DS9
NETCOM
DS1 S1
00
10
Freescale Semiconductor, Inc...
ACCESS START
FIRST TRANSFER
SECOND TRANSFER
ACCESS END
Figure 15. 32-Bit `040 READ From 16-Bit Peripheral Example
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DSW S5
DSW DSW S6 S7
DSW S8
DS5 S9
DS6
DS7
DS8
DS9
00
10
ACCESS START
FIRST TRANSFER
SECOND TRANSFER
ACCESS END
Figure 16.32-Bit `040 WRITE to 16-Bit Peripheral Example
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 18 Go to: www.freescale.com 18
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MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0
S0
00
Freescale Semiconductor, Inc...
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 17. 32-Bit `040 READ From 32-Bit Peripheral Example
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DS5 S5
DS6
DS7
DS8
DS9
00
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 18. 32-Bit `040 WRITE to 32-Bit Peripheral Example
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 19
MC68150
MOTOROLA 19
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 SW DSW SW DSW S4 DS5 S5 DS6 DS7
NETCOM
BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0
S0
00
Freescale Semiconductor, Inc...
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 19. 32-Bit to 32-Bit Transfer With a Wait State on the Peripheral Bus (This figure purposely shows a partial transfer.)
DSW BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(16:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER 00 DSW DS0 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DSW S5
Figure 20. 32-Bit to 32-Bit Transfer With a One Cycle Delayed Start (This figure purposely shows a partial transfer.)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 20 Go to: www.freescale.com 20
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MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
NETCOM
MC68150
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DSW S5
DSW S6
DSW S7
DSW S8
DS5 S9
DS6
DS7
DS8
DS9
00
01
Freescale Semiconductor, Inc...
PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER SECOND TRANSFER ACCESS END
Figure 21. 16-Bit `040 READ From 8-Bit Peripheral Example (PA1=0)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DSW S5
DSW S6
DSW S7
DSW S8
DS5 S9
DS6
DS7
DS8
DS9
00
01
ACCESS START
FIRST TRANSFER
SECOND TRANSFER
ACCESS END
Figure 22. 16-Bit `040 WRITE to 8-Bit Peripheral Example (PA1=0)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 21
MC68150
MOTOROLA 21
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START S0 DS1 S1
Freescale Semiconductor, Inc.
DS3 S3 DS4 S4 DSW S5 DSW S6 DSW S7 DSW S8 DS5 S9 DS6 DS7 DS8 DS9
NETCOM
DS2 S2
10
11
Freescale Semiconductor, Inc...
FIRST TRANSFER
SECOND TRANSFER
ACCESS END
Figure 23. 16-Bit `040 READ From 8-Bit Peripheral Example (PA1=1)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DSW DSW S5 S6
DSW DSW S7 S8
DS5 S9
DS6
DS7
DS8
DS9
10
11
ACCESS START
FIRST TRANSFER
SECOND TRANSFER
ACCESS END
Figure 24. 16-Bit `040 WRITE to 8-Bit Peripheral Example (PA1=1)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 22 Go to: www.freescale.com 22
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MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 S0
00
Freescale Semiconductor, Inc...
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 25. 16 Bit `040 READ From 16-Bit Peripheral Example (PA1=0)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DS5 S5
DS6
DS7
DS8
DS9
00
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 26. 16-Bit `040 WRITE to 16-Bit Peripheral Example (PA1=0)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 23
MC68150
MOTOROLA 23
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 S0
10
Freescale Semiconductor, Inc...
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 27. 16-Bit `040 READ From 16-Bit Peripheral Example (PA1=1)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 10 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 28. 16-Bit `040 WRITE to 16-Bit Peripheral Example (PA1=1)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 24 Go to: www.freescale.com 24
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 S0
00
Freescale Semiconductor, Inc...
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 29. 16-Bit `040 READ From 32-Bit Peripheral Example (PA1=0)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DS5 S5
DS6
DS7
DS8
DS9
00
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 30. 16-Bit `040 WRITE to 32-Bit Peripheral Example (PA1=0)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 25
MC68150
MOTOROLA 25
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:16) [READ] D(15:0) [READ] TA PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 S0
10
Freescale Semiconductor, Inc...
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 31. 16-Bit `040 READ From 32-Bit Peripheral Example (PA1=1)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DS5 S5
DS6
DS7
DS8
DS9
10
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 32. 16-Bit `040 WRITE to 32-Bit Peripheral Example (PA1=1)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 26 Go to: www.freescale.com 26
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA PA(1:0) S0 DS1 S1 DS2 S2
Freescale Semiconductor, Inc.
DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
00
Freescale Semiconductor, Inc...
PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END
Figure 33. 8-Bit `040 READ From 8-Bit Peripheral Example (PA1,PA0=00)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 00 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 34. 8-Bit `040 WRITE to 8-Bit Peripheral Example (PA1,PA0=00)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 27
MC68150
MOTOROLA 27
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
01
FIRST TRANSFER
ACCESS END
Figure 35. 8-Bit `040 READ From 8-Bit Peripheral Example (PA1,PA0=01)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 01 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 36. 8-Bit `040 WRITE to 8-Bit Peripheral Example (PA1,PA0=01)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 28 Go to: www.freescale.com 28
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
10
FIRST TRANSFER
ACCESS END
Figure 37. 8-Bit `040 READ From 8-Bit Peripheral Example (PA1,PA0=10)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 10 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 38. 8-Bit `040 WRITE to 8-Bit Peripheral Example (PA1,PA0=10)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 29
MC68150
MOTOROLA 29
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
11
FIRST TRANSFER
ACCESS END
Figure 39. 8-Bit `040 READ From 8-Bit Peripheral Example (PA1,PA0=11)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 11 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 40. 8-Bit `040 WRITE to 8-Bit Peripheral Example (PA1,PA0=11)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 30 Go to: www.freescale.com 30
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
00
FIRST TRANSFER
ACCESS END
Figure 41. 8-Bit `040 READ From 16-Bit Peripheral Example (PA1,PA0=00)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 00 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 42. 8-Bit `040 WRITE to 16-Bit Peripheral Example (PA1,PA0=00)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 31
MC68150
MOTOROLA 31
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
01
FIRST TRANSFER
ACCESS END
Figure 43. 8-Bit `040 READ From 16-Bit Peripheral Example (PA1,PA0=01)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 01 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 44. 8-Bit `040 WRITE to 16-Bit Peripheral Example (PA1,PA0=01)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 32 Go to: www.freescale.com 32
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
10
FIRST TRANSFER
ACCESS END
Figure 45. 8-Bit `040 READ From 16-Bit Peripheral Example (PA1,PA0=10)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 10 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 46. 8-Bit `040 WRITE to 16-Bit Peripheral Example (PA1,PA0=10)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 33
MC68150
MOTOROLA 33
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
11
FIRST TRANSFER
ACCESS END
Figure 47. 8-Bit `040 READ From 16-Bit Peripheral Example (PA1,PA0=11)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 11 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 48. 8-Bit `040 WRITE to 16-Bit Peripheral Example (PA1,PA0=11)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 34 Go to: www.freescale.com 34
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
00
FIRST TRANSFER
ACCESS END
Figure 49. 8-Bit `040 READ From 32-Bit Peripheral Example (PA1,PA0=00)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 00 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 50. 8-Bit `040 WRITE to 32-Bit Peripheral Example (PA1,PA0=00)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 35
MC68150
MOTOROLA 35
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
01
FIRST TRANSFER
ACCESS END
Figure 51. 8-Bit `040 READ From 32-Bit Peripheral Example (PA1,PA0=01)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 01 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 52. 8-Bit `040 WRITE to 32-Bit Peripheral Example (PA1,PA0=01)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 36 Go to: www.freescale.com 36
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
DS0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
NETCOM
MC68150
BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA
S0
READ THROUGH TRANSCEIVER
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
10
FIRST TRANSFER
ACCESS END
Figure 53. 8-Bit `040 READ From 32-Bit Peripheral Example (PA1,PA0=10)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 ACCESS START FIRST TRANSFER ACCESS END 10 S0 DS1 S1 DS2 S2 DS3 S3 DS4 S4 DS5 S5 DS6 DS7 DS8 DS9
Figure 54. 8-Bit `040 WRITE to 32-Bit Peripheral Example (PA1,PA0=10)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 37
MC68150
MOTOROLA 37
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
MC68150
Freescale Semiconductor, Inc.
NETCOM
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:24) D(23:16) D(15:8) D(7:0) [READ] TA S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DS5 S5
DS6
DS7
DS8
DS9
READ THROUGH TRANSCEIVER
Freescale Semiconductor, Inc...
PA(1:0) PD(31:24) [READ] PD(23:16) [READ] DS UWE, LWE, SWE DSACK1 DSACK0 ACCESS START
11
FIRST TRANSFER
ACCESS END
Figure 55. 8-Bit `040 READ From 32-Bit Peripheral Example (PA1,PA0=11)
DS0 BCLK CS TRANSFER CONTROLS R/W D(31:0) [WRITE] TA PA(1:0) PD(31:24) [WRITE] PD(23:16) [WRITE] DS, SWE UWE LWE DSACK1 DSACK0 S0
DS1 S1
DS2 S2
DS3 S3
DS4 S4
DS5 S5
DS6
DS7
DS8
DS9
11
ACCESS START
FIRST TRANSFER
ACCESS END
Figure 56. 8-Bit `040 WRITE to 32-Bit Peripheral Example (PA1,PA0=11)
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MOTOROLA For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 38 Go to: www.freescale.com 38
High Performance Frequency Control Products -- BR1334
MC68150
MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Semiconductor, Inc.
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PACKAGE CASE 779-02 ISSUE C
NETCOM
MC68150
B -NY BRK D Z -L-MU
0.007 (0.180)
M
T L -M
M
S
N
S
S
0.007 (0.180)
T L -M
N
S
Freescale Semiconductor, Inc...
W D
68 1
X VIEW D-D
V
G1 0.010 (0.250)
S
T L -M
S
N
S
A
0.007 (0.180)
M
T L -M
S
N
S
H 0.007 (0.180) K1
M
T L -M
S
N
S
Z
R
0.007 (0.180)
M
T L -M
S
N
S
K E C G G1 0.010 (0.250)
S
0.004 (0.100) J VIEW S T L -M
S
F 0.007 (0.180) VIEW S
DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.985 0.995 0.985 0.995 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.950 0.956 0.950 0.956 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.910 0.930 0.040 MILLIMETERS MIN MAX 25.02 25.27 25.02 25.27 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 24.13 24.28 24.13 24.28 1.07 1.21 1.07 1.21 1.07 1.42 0.50 2 10 23.12 23.62 1.02 M
-T-
SEATING PLANE
T L -M
S
N
S
N
S
NOTES: 1. DATUMS L , M , AND N DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM T , SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
IDTTM 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer High Performance Frequency For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Control Products -- BR1334 Go to: www.freescale.com 39
MC68150
MOTOROLA 39
MC68150 MPC92459 PART NUMBERS 32-Bit to 32/16/8-Bit Dynamic READ/WRITE TITLE 900 MHzPRODUCT NAME AND DOCUMENTBus Sizer INSERT Low Voltage LVDS Clock Synthesizer
NETCOM NETCOM
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Asia Pacific and Japan
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Europe
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX

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